Testing of integrated circuits

ABSTRACT

An integrated circuit with a test interface contains a boundary scan chain with cells ( 14 ) coupled between a test data input (TDI) and output (TDO) in a shift register structure. Each cell ( 14 ) is also coupled between a respective one of the terminals ( 16 ) and the core circuit ( 10 ). A test control circuit (TAP_C) supports an instruction to switch the boundary scan chain to a mode in which mode selectable first ones of the cells ( 14 ) transport data serially along the boundary scan chain while selectable second ones of the cells ( 14 ) write or read data that has been or will be transported through the first ones of the cells ( 14 ) in the further mode to or from the terminals ( 16 ) from or to the scan chain.

The invention relates to integrated circuits, and in particular tointegrated circuits with a test interface with a boundary scan path,such as the test interface defined by the IEEE1149.1 standard.

The IEEE1149.1 standard defines a test access interface for integratedcircuits. This interface permits testing of connections on a circuitboard that contains the integrated circuits. The interface is called theTAP port (Test Access Port) and comprises a Test Data Input (TDI), aTest Data Output (TDO), a Test Clock Input (TCK), a Test Mode Selectinput (TMS), and a test state reset input (TRST). The TDI and TDOterminals of different integrated circuits are coupled in a daisy chainon a circuit board. The TCK, TMS and TRST inputs of the differentintegrated circuits are coupled in parallel.

The integrated circuit with the test interface is provided with a numberof boundary scan cells coupled between the functional terminals of theintegrated circuit and the core circuit of the integrated circuit. Inaddition, the boundary scan cells are coupled to each other to form ashift register structure for test access. A test controller (called TAPcontroller) controls operation of the boundary scan cells.

The standard defines a state machine operation of the TAP controller.State transitions are selected through the TMS input. Different statetransitions provide entering and leaving a test mode. In the test mode,the boundary scan cells intercept signals between the core circuit andthe terminals. Output cells supply test signals to the terminals insteadof the core circuit and input cells capture data from the terminals. Thestates of the state machine provide for a shift state in which data isshifted from the test data input to the test data output via a chain ofboundary scan cells. At specific state transitions, data that has beenshifted through the chain is used to update test data that is output tothe terminals, and at other transitions, data from the terminals iscaptured for transport through the chain.

In addition, the TAP controller provides for the application of commandsthrough the TDI terminals. The commands may be used to switch specificintegrated circuits to different submodes of the test mode, including anormal EXTEST mode in which test data can be shifted through theboundary scan cells and signals between the terminals and the core areintercepted, a bypass mode in which data is shifted from TDI to TDObypassing the boundary scan cells in the integrated circuit, afunctional mode in which the integrated circuit connects normally to itsterminals while other integrated circuits are in test mode, and a CLAMPmode in which the integrated circuit disables updating of the datasupplied from the boundary scan cells. In further modes, the test datais routed from the test data input TDI to the test data output TDOthrough internal scan chains selected by the instructions.

A serial shift register structure that runs through all boundary scancells and, via the TDO-TDI connections, from one integrated circuit toanother has advantages and disadvantages. The main advantage is that thewiring needed to supply test data to different integrated circuit can beminimized. The main disadvantage is that the serial structure slows downthe speed with which the terminals of the integrated circuits can beaccessed.

The slow access speed is partly addressed by providing bypass and clampinstructions. Bypass instructions supplied to selected integratedcircuits effectively remove the boundary scan chains of selectedintegrated circuits from the overall chain on the printed circuit boardand thus reduce the number of clock cycles needed to transport test datato or from a relevant boundary scan cell. The clamp instruction makes itpossible to supply more useful data within the same number of clockcycles, because the signals at the terminals of all irrelevantintegrated circuits are kept fixed and require no test data. As aresult, data for successive updates of the relevant integrated circuitmay be supplied instead of those for irrelevant integrated circuits.However, known instructions to set the integrated circuit for the bypassmode or the clamp mode apply to the integrated circuit as a whole, tobypass or clamp the scan chain as a whole.

The prior art has proposed further solutions to improve the access speedduring testing. U.S. Pat. No. 6,430,718, for example, has proposed anintegrated circuit wherein test data can be entered into a plurality ofboundary scan cells in parallel from automated test equipment that isconnected to a number of terminals in parallel. The test data issubsequently shifted to internal scan cells where it is used for testpurposes. Depending on the instructions, the internal scan cells eitherreceive test data from the test data input TDI directly or from theboundary scan cells to which the automatic test equipment is connected.Supplying test data in parallel increases the speed. Similarly, testresults may either be passed to a number of terminals in parallel from aplurality boundary scan cells or fed to the test data output.

U.S. Pat. No. 6,018,815 also proposes to enter test data in parallel,but in this case via a number of dedicated terminals. This publicationalso proposes to provide a number of scan chains and test controllerinstructions to select which of these scan chains is coupled between thetest data input TDI and the test data output TDO, as well as aninstruction to couple all scan chains in series between the test datainput TDI and the test data output TDO.

The proposed speed improvements, in terms of bypass instructions,clamping instructions, and instructions for parallel input andreconfiguration of the scan, aim at reducing the amount of time neededto pass data to or from terminals during testing. Not related toimprovements of access speed, U.S. Pat. No. 5,991,908 discloses a familyof FPGAs (Field Programmable Gate Arrays) and a hardwired device (a maskprogrammable circuit) that can emulate the operation of the FPGAs fromany one of the family. The hardwired device is used to replace the FPGAsin circuit modules that have been sufficiently developed to permit massmanufacture without further design changes. Both the FPGAs and thehardwired device are provided with a boundary scan interface. Circuitboards that contain either the FPGA or the hardwired version are testedin the same way. However, since different FPGAs in the family havedifferent numbers of terminals, which, moreover can be programmed asinput or output terminals, it is necessary to reconfigure the boundaryscan chain in the hardwired device so as to match that of the emulatedFPGA. Obviously, this type of reconfiguration has to be performed onlyonce, when the FPGA is programmed, presumably in the same way as thebulk of the FPGA is programmed. No more dynamic reconfiguration isdescribed.

The Test Access Port has been more and more explored for use other thanjust structural testing. For programming Flash devices and PLDs it isalready common to use the TAP for access. The five-pin connector isalready on the PCB for structural testing, so additional connectors forprogramming are not needed, saving board space. The present inventionconsiders the use of the TAP and the boundary scan implementation fordesign debug during prototyping and other types of access where a highthroughput is required.

Development of an application or system consists of several stages. Oneof these stages is the development of the actual design for a consumerapplication like TV or DVD. Before full production starts, prototypeswill be developed. During prototyping, testing of the applicationcomprises at least the following:

Electrical interconnection tests, often referred to as structural tests.The IEEE1149.1 standard is nowadays a well recognized and appreciatedstandard for structural testing of PCBs.

Functional tests will validate board interconnections that cannot beresolved in structural tests.

Debugging the actual design. During debugging, the functionality of theapplication (for example a TV or DVD) can be checked. This design debugphase is typical of prototyping where the actual design is not fixedyet. Here, incorrectnesses in the design can be remedied. When theapplication is in full production, debugging is not required anymore andfunctional and structural tests will validate the design'sfunctionality.

During prototyping, board level debug is meant to eliminate designerrors. This is an important step before production can start. Here, thefocus will be on aspects like:

-   -   design faults in the system,    -   board layout faults    -   software faults    -   chip design faults in the application.

All these aspects are important in the total design debug step toevaluate correct functioning.

If design debug is to be done fast and efficiently, access to the ICs isof prime importance. Traditionally, this is done by contacting theavailable connectors on the PCB to monitor the data. Many functionaldata streams can be investigated in the traditional way. However, datastreams not available at connectors can be important as well to bevalidated during prototyping. As the use of small outline packages andBGA grows rapidly, it is more and more difficult to perform measurementson the PCB. Probe access to these pins is then not obvious at all.Besides, the strong pressure on the cost of producing PCBs causes theapplication to take less surface on the board. Adding additional testspots for use with test needles is often not feasible. For this reasondesigners are looking for a trade-off between board space and theincreasing programming and debug access capabilities required for ICs.Currently, data streams not accessible through standard devices cannotbe validated, or it is at least very difficult to do so.

This design debug stage is a time-consuming and therefore an expensivepart in the total cycle of product creation. Much expensive time is lostwhen looking for errors in a design that cannot be located owing toaccess problems. Other means of access and monitoring must be created tomonitor data streams on these chips.

Debugging of the system also requires access through connectors or testpoints. Using the TAP port has already been demonstrated for chip leveldebug as well as for debugging software using the EJTAG port. Using theTAP port for board level debug of the design functionality is a logicalextension. The implemented boundary scan architecture, which has contactto every IO pin of an IC, enhances the access to other pins. In theprototyping stage this makes it possible to monitor data streams tootherwise inaccessible pins without having to incorporate additionalboard design.

The Standard Boundary Scan test puts the application in the test domain,not in the functional domain. This avoids that functional data arepassed through the chain towards the TAP connector or other pins in theapplication.

In principle, when one IC is put in EXTEST mode and all others are setto functional mode by using the BYPASS instruction, TDO can be used asan observer for functional data and TDI as a driver. The TAP connectedto the IC carrying the debug data stream should be selected. Forspecific situations where predefined values must be put on pins, theseICs need to be set in CLAMP while the IC that transfers the data to theTAP needs to be in EXTEST.

The fundamentally static behavior of Boundary Scan, however, restrictsthe use for functionally by driven test or debug. The serial nature ofthe boundary scan chain reduces the effective clock frequency on thedigital pins. Although the test frequency (TCK) is generally in therange of 10-20 MHz, most ASIC designs will have chains with 1000 cells,reducing the speed on IC pins (data rate) effectively to 10 kHz. Formost (consumer) applications like DVDR and digital TV, 10 kHz can beconsidered as almost static. Usually this low frequency does not sufficefor proper and reliable debugging of the functional features, whichrequires much higher speeds. Bypassing cells in the chain not requiredfor performing the specific debug test can increase the effective speed.Besides, all pins of the IC are either in functional mode or in boundaryscan mode when the normal boundary scan is performed.

It is an object of the invention to improve the suitability of a testinterface of an integrated circuit for use in debugging.

It is another object of the invention to increase the access speed atwhich selected terminals in circuits can be accessed via a boundary scanchain.

The invention provides an integrated circuit according to claim 1.According to the invention, an integrated circuit which has a boundaryscan chain for testing purposes supports a further mode, to which it canbe switched by an instruction. The further mode is designed for debugpurposes, but without deviating from the invention it may be used forother purposes that require efficient access. In the further mode,selectable first ones of the cells transport data serially along theboundary scan chain while selectable second ones of the cells write orread data that has been or will be transported through the first ones ofthe cells respectively in the further mode to or from the terminals fromor to the scan chain. The first ones of the cells do not read or writedata from or to the terminals in the further mode.

This is preferably realized by providing a multiplexing circuit thatpermits the first ones of the cells to be bypassed in the shift registerstructure in the further mode, when the second ones of the cells outputor input data from or to the shift register structure, directly from theshift register structure or after latching in a scan flip-flop or anupdate flip-flop of the second one of cell.

Preferably, cells are selected to be first or second ones of the cellsby means of configuration information that is loaded into configurationcells via the test interface.

Preferably, there is a configuration cell for each respective boundaryscan cell, so that each boundary scan cell that supports the furthermode can be selected to be a first or second one of the cellsindividually, independently of the other cells.

In a further embodiment, the update flip-flops of the boundary scancells are used as configuration cells. During normal testing, updateflip-flops function to supply test data to the functional output of thescan cell, but in the further mode they function to select whetherindividual cells operate as first or second ones of the cells.

In a first embodiment, the boundary scan chain can pass signalsasynchronously in the further mode, without latching in the shiftregister structure. Data is read directly from selected terminals and/orwritten to those terminals and passed transparently along the scan pathwithout being latched.

In a second embodiment, the boundary scan chain operates synchronouslyin the further mode, so that input data is latched before being passedthrough the boundary scan chain in the further mode and/or output datais latched before being output from the boundary scan chain.

In a further embodiment, the integrated circuit supports both modes, andan instruction to select in which mode the integrated circuit willoperate.

These and other objects and advantageous aspects of the invention willbe described in more detail with reference to the following Figures

FIG. 1 shows the architecture of an integrated circuit,

FIG. 2 shows an input block for use in a boundary scan chain,

FIG. 3 shows an output block for use in a boundary scan chain,

FIG. 4 shows a further block for use in a boundary scan chain,

FIG. 5 shows an input block for use in a boundary scan chain,

FIG. 6 shows an output block for use in a boundary scan chain,

FIG. 7 shows an input block for use in a boundary scan chain,

FIG. 8 shows an output block for use in a boundary scan chain, and

FIG. 9 shows a debug system

When developing the first conceptual implementation, it is chosen to usestandard boundary scan cells as defined by the IEEE1149.1 standard. Theextension required is built around these standard cells. The extensionto the basic architecture is the same for both modes. The differenceoccurs at cell or chip pin level and will be explained in the next twosections.

FIG. 1 shows the extended architecture of an integrated circuit (IC)chip, using the TAP port for access to the chip, and the boundary scancells for access to the specific IC pins. The integrated circuitcomprises a core circuit 10, external terminals 16, and a plurality ofboundary scan blocks 12. Each boundary scan block 12 has a scan inputSI, a scan output SO, a functional input PI, and a functional output PO(indicated for one block only for the sake of clarity). The boundaryscan blocks 12 are coupled in a boundary scan chain in that the SO andSI of successive blocks are interconnected. Blocks 12 connect the corecircuit 10 to the terminals 16 with the functional inputs and outputsPI, PO. Depending on whether the terminal is used as input or output,the functional input PI or the functional output PO of the scan block 12is coupled to the terminal and the functional output PO or thefunctional input PO is coupled to the core circuit.

The integrated circuit has conventional P1149.1 test terminals TDI, TDO,TCK, TMS and TRST, and a TAP (Test Access Port) controller (TAP-C)coupled to the boundary scan blocks 12. For the sake of clarity, controlconnections to the blocks for conventional P1149.1 control are notshown. TAP controller TAP-C has outputs for signals CTL and MODE thatare coupled in parallel to all boundary scan blocks 12.

The integrated circuit also contains a chain of configuration cells 14,which may be implemented as conventional scan cells. The chain ofconfiguration cells is coupled between the test data input TDI and thetest data output in parallel with the boundary scan chain. Under thecontrol of instructions, TAP controller TAP_C controls which chainreceives and transmits data between TDI and TDO. TAP controller TAP-Csupplies a HOLD signal to configuration cells 14.

Each configuration cell 14 has a configuration signal output coupled toa configuration input of a respective one of the boundary scan blocks12. Thus, the boundary scan blocks 12 receive common signals CTL andMODE and block-specific configuration signals.

Two modes (synchronous and asynchronous) are implemented in the samearchitecture. Two new private instructions are created in theinstruction register of the boundary scan TAP controller, one for thesynchronous mode (SYNC) and one for the asynchronous mode (ASYNC). Theseinstructions select the required mode. A separate configuration register(the config cells) equal in length to the boundary scan chain is used tocontrol each boundary scan cell block (BS block). The BS block is a partconsisting of a standard boundary scan cell with additional logic neededfor the debug modes. The configuration register holds the setting foreach active and inactive pin for debug. Active refers to read and writeaccess on the IC pin, inactive to not having read and write access.Control signals are required to make both modes possible. FIG. 1 onlyshows the additional control signals needed for this implementation.Control is achieved by global control lines (CTL, MODE, HOLD) and bylocal, cell-specific control lines (CFG(i)). The global control linesCTL and MODE are routed from the TAP controller to each BS block. HOLDis routed from TAP controller to each cell of the configurationregister. The local lines CFG(i) are BS block-specific and routedbetween the BS block and the controlling cell of the configurationregister.

Principle of Operation

When a mode is chosen, the configuration is loaded into the fullconfiguration (shift) register. CFG(i)=“1” indicates that the specificBS block will read or write functional data from the IC pin. A “0”indicates the opposite, the BS block is bypassed and no data is read orwritten from the IC pin. The HOLD signal guarantees that theconfiguration setting will not change during testing. Afterconfiguration the mode will be chosen by selecting the correct privateinstruction (SYNC or ASYNC). Either instruction will put the correctvalues on the global signals CTL and MODE. CTL guarantees that the totalimplementation still conforms to IEEE1149.1, MODE determines SYNC orASYNC mode. The table below shows the required values for differentsituations.

Mode CTL MODE CFG(i) SYNC 1 0 0/1 ASYNC 1 1 0/1 EXTEST 0 0 XInput Pins and Output Pins

The BS block itself determines how the specific mode is incorporated inthe cell design. For this extended architecture, the additional logicsurrounds the basic boundary scan cell. The standard boundary scan celldesign is not changed for the purpose of prototyping. The standardboundary scan protocol for the state machine is also used for the twonew modes. For this reason the values for C0-C3 are determined byautomated boundary scan implementation software.

FIG. 2 shows the actual design for an input boundary scan block. Element20 is a standard boundary scan input cell, with inputs coupled to a scaninput SI and a functional input PI (coupled to an external terminal ofthe IC) and outputs coupled to a scan output SO and a functional outputPO coupled to a core circuit of the IC. Decode logic 22 is provided forgenerating the control signals. In addition, only two multiplexers 24,26 are used to create the proper routing of the test signals for bothmodes.

The standard boundary scan cell 20 comprises an input multiplexingcircuit 200, 202, a scan flip-flop SFF, an update multiplexer 206, anupdate flip-flop UFF, and an output multiplexer 209. Scan input SI,functional input PI, and an output of scan flip-flop SFF are coupled toinputs of first multiplexing circuit 200, 202. Multiplexing circuit 200,202 has an output coupled to a data input of scan flip-flop SFF. Updatemultiplexer 206 has inputs coupled to a data output of scan flip-flopSFF and an output of update flip-flop UFF. Update multiplexer 206 has anoutput coupled to a data input of update flip-flop UFF. Outputmultiplexer 209 has inputs coupled to functional input PI and a dataoutput of update flip-flop UFF. Output multiplexer 209 has an outputcoupled to functional data output PO. Scan flip-flop SFF and updateflip-flop UFF are clocked from test clock input TCK. First multiplexingcircuit 200, 202 is controlled by signals C0, C1 from the TAPcontroller, update multiplexer 206 is controlled by a signal C2 from theTAP controller, and output multiplexer 209 is controlled by a signal C3from the TAP controller. C0-3 are standard IEEE 1149.1 signals, used toswitch boundary scan cell 20 to various modes of operation.

Scan flip-flop SFF may comprise a series connection of two flip-flopswhich load data from their inputs at mutually opposed clock transitionsof the test clock TCK. Alternatively, the first one of these flip-flopsmay be placed anywhere in the path from the scan input SI to scanflip-flop SFF, but not in the connection between the scan input SI andfirst additional multiplexer 24.

First additional multiplexer 24 has inputs coupled to functional datainput PI and to scan input SI. Second additional multiplexer 26 hasinputs coupled to an output of first additional multiplexer 24 and thedata output of scan flip-flop SFF. An output of second additionalmultiplexer 26 is coupled to scan output SO. It will be appreciated thatadditional multiplexers 24, 26 function as a three-input multiplexingcircuit, which can couple any of its inputs to its output. Withoutdeviating from the invention, other multiplexing circuits may be usedfor this purpose.

Decode logic 22 has inputs for a control signal CTL, a mode selectionsignal MODE, and a configuration signal CFG(i) for the block. Decodelogic 22 feeds the logic OR of CFG(i) and the inverse of CTL to acontrol input of first additional multiplexer 24. Decode logic 22 feedsa further logic OR of the inverse of this logic OR and the logic AND ofthe MODE signal and the configuration signal to the control input ofsecond additional multiplexer.

The reader can easily verify, using the table, that normal EXTEST isstill compliant with the standard. That is, when decode logic setssecond additional multiplexer 26 to pass the output signal from scanflip-flop SFF, the circuit will operate as a conventional boundary scancell.

In FIG. 3 the actual design for an output block is shown. Here thefunctional input is coupled to the core circuit and the functionaloutput is coupled to the external terminal. The output block contains astandard boundary scan cell 20 and decode logic 22, which are identicalto those of the input block. Compared with the input block, the firstadditional output multiplexer is omitted from the output block, thesecond additional multiplexer 26 having inputs coupled to scan input SIand the data output of scan flip-flop of the boundary scan cell. Inaddition, a further output multiplexer 37 and a tri-state buffer 38 areincluded. The output of output multiplexer 209 and the scan input SI arecoupled to the inputs of further output multiplexer 37, which has anoutput coupled to functional output PO via tri-state buffer 38. Thecontrol signal of further output multiplexer 37 is the MODE signal.Tri-state buffer 38 is controlled by the logic OR of CFG(i) and theinverse of CTL. The tri-state buffer 38 is added to make the connectedIC pin tri-state. By taking CFG(i)=0 the pin is set inactive. For thisdesign of the output block it can be verified that EXTEST is stillcompliant with the standard.

The next two sections will discuss the operation of the input and outputpin for each mode in more detail.

Synchronous Mode—Reconfigurable Boundary Scan

The synchronous mode is strongly related to normal boundary scan. Themain difference is that the standard chain length will be adapted to thedebug situation. This can be done in-circuit and provides thepossibility to have several independent data streams over one or morepins. The effective transfer speed is higher compared with a normalboundary scan because of the reconfigurable character of the chain.

Considering FIG. 2 again, the operation of the block in SYNC mode can beunderstood. The specific pin can be set active (used for data streams)or inactive (not used for data streams) with the configuration signalCFG(i). The Table shows the values on the multiplexers A and B thatcreate the required paths.

Input cell Mux. A Mux. B CFG(i) Active 1 0 1 Inactive 0 1 0

The table shows that a transparent path is created from SI to SO whenthe cell is set inactive. When active, SFF is used to create a path fromPI to SO and UFF puts the data to the core (as defined by IEEE1149.1).With the normal boundary scan state machine protocol for the cell, thelatter path is a normal boundary scan path.

For output cells the table below is valid (see also FIG. 3).

Output cell Mux. A Mux. B Buffer ENA CFG(i) Active 0 0 1 1 Inactive 0 10 0

When the cell is active, normal clocking by the state machine is used. Apath from SI through the boundary scan cell to PO is created. The bufferis enabled. When inactive, the same transparent path from SI to SO iscreated as for the input cell. The buffer is tri-stated.

The character of this implementation is one of a reconfigurable boundaryscan chain.

Data Rate Over the IC Pins

The advantage of adapting the chain in-circuit to a few cells is thatthe effective data rate or transfer frequency on the IC pin isincreased.

To understand this, consider a chip with 100 boundary scan cells, a TCKfrequency of 20 MHz, and one single pin set active. For standard EXTESTit takes 104 TCK cycles to put the first data bit on the active pin.About 4 TCK cycles are used for the state machine and 100 TCK cycles areneeded to shift through the chain. This equals a data transfer rate of0.2 MHz.

Using a reconfigurable boundary scan chain, the configuration will besuch that this specific cell/pin is the only cell in the chain. Thisreduces the chain length from 100 cells to a single cell. The increasein the effective data rate is obvious. Once again, 4 cycles for thestate machine but only 1 for shifting, providing a frequency of 20/5=4MHz on the pin. Moreover, when 6 pins are selected, the frequencybecomes 20/10=2 MHz. In the limit the normal boundary scan chain isselected with its low speed (with all characteristics of normal boundaryscan). This frequency range (1-5 MHz) is often suitable for testingfunctionality of a design. It is to be noted that one or twomultiplexers in the scan path do not limit the effective speed, but dolimit speed many consecutive cells are inactive. In that case each cellwill add one or two multiplexers to the scan path. Then, for correctclocking in synchronous mode the total delay of these multiplexers cannot exceed ½TCK.

Data Streaming on IC Pins

In the synchronous mode the normal clocking protocol as defined byIEEE1149.1 is used. Similar to normal structural testing, thesynchronous mode can read and write different data streams on differentpins. The use of a reconfigurable chain by this mode makes it possiblethat cells/pins that are not selected for testing are transparentlyrouted from SI to SO. While the total length of the chain is reduced,each active pin will behave in conformity with the standard protocol.The selected chain is loaded with data followed by an update stage. Thisprocess is repeated for longer data streams. Each active pin can carrydifferent data.

Asynchronous Mode—Direct Data Streaming

The asynchronous mode is of importance when speed is the key issueduring testing. This mode is quite different from the synchronous modesince it does not use the actual boundary scan cell. Data is directlyread or written from the IC pin and directly transferred towards thescan path. Any path created is a transparent path. The settings forinput cells are shown in the Table below (see also FIG. 2).

Input cell Mux. A Mux. B CFG(i) Active 1 1 1 Inactive 0 1 0

The operation is straightforward. Multiplexer B is always “1” since theboundary scan cell output is never used. Multiplexer A creates atransparent path from SI to SO when the cell is inactive and a path fromPI to SO when the cell is active. The Table below is valid for outputcells (see also FIG. 3).

Output cell Mux. A Mux. B Buffer ENA CFG(i) Active 1 1 1 1 Inactive 1 10 0

When the cell is inactive, a path from SI to SO is created with atri-stated buffer. When active, the buffer is enabled and thetransparent path SI to SO is created to allow that data is directlypassed to other pins as well.

Data Rate Over the IC Pins

Clocking is avoided in the asynchronous mode. This provides anopportunity to go beyond the limits of the normal boundary scan TCKfrequency. In fact once in this mode with the correct settings, the scanpath is free for any digital functional data. The data is read orwritten to the IC pin in real time. The data rate is mainly limited bythe test signal. If this signal comes from a JTAG tester, it isgenerally limited to 20 MHz. If real-time data from another chip on theboard is tested, however, the limit is theoretically determined byfunctional design. As in the synchronous mode, delay introduced by themultiplexers in the scan path is present. Nevertheless, this delay willnot be critical for debug here because clocking is not an issue.

Data Streaming on IC Pins

In the asynchronous mode, high-speed signals can be directly transferredto the pins, but all pins will have the same data stream. This isbecause the implementation consists of parallel connections. No holdfunction for data is used as is done in the synchronous mode. Inpractice, this mode will generally be used for testing data on a singlepin. However, to place the IC in this asynchronous mode, interference bythe TAP controller is required since this controls the additionalmultiplexers. After this initialization, the selected pins are free totransfer data when the TAP controller is in the shift stage.

SECOND EMBODIMENT

In the second embodiment only a single debug mode is implemented by wayof example, which provides a bypassing of inactive cells. Instead of thecontrol signals CTL, MODE, the TAP controller supplies a control signal“STREAM” to all cells to switch the cells between the normal mode andthe debug mode.

FIG. 4 shows a second embodiment of a boundary scan block. Compared withthe input block of FIG. 2, a number of changes have been made. The firstadditional multiplexer 24 has been omitted. Additional multiplexer 26has inputs coupled to serial scan input SI and the data output of scanflip-flop SFF. The control input of additional multiplexer 26 is coupledto the output of a logic gate that produces the logic AND of theconfiguration input CFG(i) of the cell and the STREAM signal. A controlmultiplexer 40 is provided, which has inputs coupled to theconfiguration input CFG(i) and the conventional control input C3 ofoutput multiplexer 209. The output of control multiplexer 40 is coupledto the control input of output multiplexer 209. The control input ofcontrol multiplexer 40 is coupled to the STREAM input.

In operation, when “STREAM” is logically low, the block operates as anormal 1149.1 cell. When STREAM is logically high, operation depends onconfiguration signal CFG(i) of the block. Blocks that are selected to beinactive (CFG(i)=0) bypass the scan input SI to the scan output SO andthe functional input PI to the functional output. Blocks that areselected to be active (CFG(i)=1) shift data from the scan flip-flop SFFto the scan output and pass data from the update flip-flop UFF to thefunctional output.

The length of the boundary scan chain can thus be adapted by means ofthe configuration signals to eliminate inactive blocks from the chain.The active blocks can be operated as normal boundary scan cells in theshortened chain. The inactive blocks connect the terminals 16 to thecore circuit 10.

THIRD EMBODIMENT

In the third embodiment the update flip-flop of the boundary scan cellsis used to supply the configuration signal.

FIG. 5 shows the input block of the third embodiment. A conventionalboundary scan cell is used, except that a first control multiplexer 50has been added. First control multiplexer 50 has inputs coupled to theoutput of the update flip-flop UFF and the conventional P1149.1 controlinput C1 that is used to control capture of data from the functionalinput PI. The output of first control multiplexer 50 is coupled to theinput of multiplexing circuit 200, 202 that controls capture of datafrom the functional input PI. The control input of first controlmultiplexer 50 receives the STREAM signal.

FIG. 6 shows the output block of the third embodiment. Again aconventional boundary scan cell is used, except that a second controlmultiplexer 60 and an update bypass multiplexer 62 have been added. Thesecond control multiplexer 60 has inputs coupled to receive the outputsignal of update flip-flop UFF and the conventional P1149.1 signal C3that conventionally controls output multiplexer 60. A control input ofsecond control multiplexer 60 is coupled to receive the STREAM signal.Second control multiplexer 60 has an output coupled to a control inputof output multiplexer 209.

Update bypass multiplexer 62 has inputs coupled to the data output ofupdate flip-flop UFF and the data output of scan flip-flop SFF. Acontrol input of update bypass multiplexer 62 is coupled to receive theSTREAM signal. Output multiplexer 209 has inputs coupled to the outputof the bypass multiplexer and the functional data input PI.

In operation the normal boundary scan protocol is first executed to loadconfiguration data into the update flip-flops. Subsequently the normalboundary scan protocol is used to load an instruction for the TAPcontroller to set STREAM logic high. The content of update flip-flop UFFcontrols whether cells are active when the STREAM signal sets theintegrated circuit to the debug mode.

In those input cells where the content of update flip-flop UFF islogically low, scan flip-flop SFF only functions as part of the shiftregister structure and is not used to capture data from the functionalinput PI. The input cells where the content of update flip-flop UFF islogically high capture data from functional input PI at every TCK clockcycle. This is used when the TAP controller is made to assume the shiftstate repeatedly, which during normal 1149.1 testing merely serves toshift test data through the shift register structure. When STREAM islogically high and TAP controller is made to assume the shift staterepeatedly, data is captured in selected input cells in every TCK clockcycle and subsequently shifted from the input cell through the shiftregister structure.

In the output cells, when STREAM is logically high, those output cellswhere the content of update flip-flop UFF is logically low pass datafrom functional input PI to functional output PO. The output cells wherethe content of update flip-flop UFF is logically high pass data from theshift register structure to functional output PO.

In use, most update flip-flops are loaded with logically low values. Thecells in the boundary scan chain in which update flip-flop UFF is loadedwith logically high values are input and output cells alternately.

In one example, the update flip-flop UFF of only one input cell isloaded with a logically high value and the update flip-flops UFF of allother cells are set logically low. As a result data is captured in thatone input cell and transported to TDO through the chain in each TCKclock cycle when STREAM is logically high and the TAP controller is madeto assume the shift state.

In another example, the update flip-flop UFF of only one output cell isloaded with a logically high value and the update flip-flop UFF of allother cells are set logically low. As a result data supplied from TDIthrough the boundary scan chain is output from that one output cell ineach TCK clock cycle when STREAM is logically high and the TAPcontroller is made to assume the shift state.

In a further example, the update flip-flops UFF of only one output celland only one input cell are loaded with a logically high value. If theinput cell precedes the output cell in the boundary scan chain, thisresults in data capture in the input cell, followed by transport throughthe boundary scan chain and output from the output cell in every clockcycle when STREAM is logically high and the TAP controller is made toassume the shift state. Thus a stream is created from the functionalinput PI of the input cell to the functional output of the output cell,which transports one bit in every TCK cycle.

It will be appreciated that any number of such streams can be passed inparallel by setting the update flip-flops UFF of pairs of input-outputcells.

If the first cell in the boundary scan chain in which the content ofupdate flip-flop UFF is logically high is an output cell, data is passedfrom TDI to that output cell in every TCK cycle. Similarly, if the lastcell in the boundary scan chain in which the content of update flip-flopUFF is logically high is an input cell, data is passed from that inputcell to TDO in every TCK cycle.

FOURTH EMBODIMENT

Like the third embodiment, the fourth embodiment uses the updateflip-flop to control whether cells are active. In the fourth embodiment,however, the scan flip-flops are bypassed in the debug mode. This meansthat signals are passed directly along the boundary scan chain, withoutthe need to shift under control of TCK. A control signal “SHORT” isadded to control bypassing, which is issued by the TAP controller andset to logically high in response to a corresponding command.

FIG. 7 shows an input cell according to the fourth embodiment. Comparedwith the third embodiment, a bypass multiplexer 70 has been added, withinputs coupled to the data input and data output of scan flip-flop SFF,an output coupled to scan output SO of the cell, and a control inputcoupled to receive the SHORT signal.

FIG. 8 shows an output cell according to the fourth embodiment. Comparedwith the third embodiment, a bypass multiplexer 70 has been added, withinputs coupled to the data input and data output of scan flip-flop SFF,an output coupled to scan output SO of the cell, and a control inputcoupled to receive the SHORT signal. The output of bypass multiplexer isalso coupled to an input of update bypass multiplexer 62 instead of thedata output of scan flip-flop.

In operation, the conventional boundary scan protocol is first used toload configuration data into the update flip-flops. Subsequently aninstruction is supplied to the TAP controller using the conventionalboundary scan protocol to set SHORT logically high. As a result a directconnection is opened up along the boundary scan chain. In cells that areselected to be active by the configuration data, the functional input PI(if the cell is an input cell) and/or to the functional output PO (ifthe cell is an output cell) is connected to this direct connection. Thusa direct connection is set up between the functional inputs PI andfunctional outputs PO of active cells. In input cells that are notactive, the input signal from the functional input PI or the signal fromupdate flip-flop UFF is passed to the functional output, depending ontest control signal. In output cells that are not active, the inputsignal from the functional input PI is passed to the functional outputPO.

FIG. 9 shows a debug system with a number of interconnected integratedcircuits 90. Two connections 92, 94 are indicated specifically. Part ofthe integrated circuit is connected via a test interface, withdaisy-chained TDI, TDO inputs and outputs and parallel TCK, TMS, TRSTinputs (only one input shown for the sake of clarity). The inventionrenders it possible to set one or several integrated circuits 90 to thedebug mode, after which debug signals can be output and input at a highrate, or even continuously via connections 92, 94 to other integratedcircuits from the selected integrated circuit or circuits.

It will be realized that the invention is not limited to the specificembodiments disclosed in the Figures. For example, various sources maybe used to supply output signals from the functional outputs PO ofinactive cells. The embodiments show the use of signals from thefunctional input PI or signals from the update flip-flop by way ofexample. Instead, a default signal may be supplied or any otherconvenient signal. Although each embodiment shows the use of a specificsource, it should be realized that any other source may be used instead.Even a programmable selection from a plurality of sources may be used.Under some circumstances it is desirable that the entire circuitoperates functionally, except for terminals where debug signals areinjected. In this case the inactive cells preferably connect functionalinputs PI and functional outputs PO. Under other circumstances a fixedoutput is preferred, in which default signals or signals from the updateflip-flops may be used.

Furthermore, it will be realized that, although it is preferred to usethe update flip-flop of each particular cell as the configurationflip-flop for that particular cell, there is of course no objection tousing the update flip-flop of one cell as the configuration flip-flopfor another cell. Each configuration flip-flop may control configurationof a respective cell, but of course a configuration flip-flop maycontrol the configuration of a plurality of cells in parallel. Thus, atleast part of the update flip-flops need not be used as configurationflip-flops, leaving these update flip-flops free to supply programmablesignals to the functional outputs. Configuration flip-flops that do notdouble as update flip-flops may also configure multiple cells, orrelieve the update flip-flop of specific cells from configuring thecell.

Furthermore, it will be appreciated that the cells of any one of theembodiments may be arranged so as to be programmable to operate in oneof the described debug modes only or in a selectable one of a pluralityof debug modes. The invention is not limited to the use of theparticular control signals (e.g. CTL, MODE) used in the embodiments:other types of control signals may be used.

Part of the cells in the same circuit (or even in the same integratedcircuit) may be implemented according to one embodiment and another partmay be implemented according to another embodiment. In particular, forexample, the fourth embodiment may be used for a number of cells tospeed up data transport, another embodiment being used for other cellsto provide some form of pipelining. Part of the boundary scan cells mayeven be implemented completely as conventional boundary scan cells, i.e.without supporting a further mode. Thus, a further conventional boundaryscan chain may be intermingled or placed in series with the boundaryscan chain according to the invention.

Furthermore, it should be realized that the actual circuits shown in theembodiment are merely provided by way of example. For example, themultiplexing functions could be realized with various alternativecircuits. Similarly, although conventional P1149.1 test states arepreferably used to control signal generation by the TAP controller, itwill be realized that dedicated states may be used when the integratedcircuit has been switched to the debug mode.

Furthermore, it should be appreciated that, although the invention hasbeen described for debug purposes, the disclosed circuitry may be usedfor other purposes, such as programming of a non-volatile memory orprogramming of a programmable circuit such as gate arrays.

1. An integrated circuit comprising: a core circuit; terminals forcoupling the core circuit to circuitry external to the integratedcircuit, a test data input and a test data output; a boundary scan chaincomprising cells coupled between the test data input and output in ashift register structure, each cell also coupled between a respectiveone of the terminals and the core circuit, a test control circuitarranged to switch the boundary scan chain between a functional mode, inwhich the cells permit signal flow between the terminals and the corecircuit, and a test mode, in which test data is shifted serially throughthe cells along the boundary scan chain and in which the cells interceptsignal flow between the respective ones of the terminals and the corecircuit, wherein the test control circuit is arranged to execute aninstruction to switch the boundary scan chain to a further mode, inwhich further mode selectable first ones of the cells transport dataserially along the boundary scan chain while selectable second ones ofthe cells write or read data that has been or will be transportedthrough the first ones of the cells in the further mode to or from theterminals from or to the scan chain.
 2. An integrated circuit accordingto claim 1, comprising configuration cells for respective cells of theboundary scan chain, the configuration cells being loadable withconfiguration data from the test data input, each cell of the boundaryscan chain having a configuration input coupled to its configurationcell for selecting whether the cell of the boundary scan chain has tofunction as one of the first ones or one of the second ones of the cellsunder the control of the configuration data.
 3. An integrated circuitaccording to claim 2, wherein each of the cells of the boundary scanchain comprises a scan flip-flop and an update flip-flop, the scanflip-flops of successive cells in the boundary scan chain being coupledserially to form the shift register structure, the update flip-flop ofthe cell being coupled to the shift register structure to receive testdata from the scan flip-flop, the update flip-flop supplying the testdata to the respective one of the terminals to which the cell is coupledin the test mode, and wherein the update flip-flop of at least part ofthe cells function as said configuration cells to supply configurationdata in the further mode.
 4. An integrated circuit according to claim 3,each cell of the boundary scan chain comprising a multiplexing circuitwith inputs coupled to the shift register structure and to the corecircuit, an output coupled to the terminal for the cell, and a controlinput coupled to the test control circuit and to an output of the updateflip-flop of the cell, so that in the further mode the multiplexingcircuit couples the core circuit to the terminal when the updateflip-flop indicates that the cell is a first one of the cells and themultiplexing circuit couples the shift register structure to theterminal when the update flip-flop indicates that the cell is a secondone of the cells.
 5. An integrated circuit according to claim 1, whereineach cell comprises: a scan input (SI) and a scan output, the test datainput being coupled to the scan input (SI) of a frontmost one of thecells in the boundary scan chain, each further one of the cells havingits scan input coupled to the scan output of a preceding one of thecells, and a final one of the cells having its scan output (SO) coupledto the test data output; a scan flip-flop having an input coupled to thescan input (SI) of the cell; a multiplexing circuit comprising inputscoupled to the scan input of the cell and to an output of the scanflip-flop, the multiplexing circuit having an output coupled to the scanoutput of the cell and to a control input; a configuration input coupledto the control input of the multiplexing circuit for selecting that themultiplexing circuit couples the scan input to the scan output in thefurther mode if the cell is selected to be a first one of the cells. 6.An integrated circuit according to claim 5, wherein each cell has afunctional input coupled to an input of the scan flip-flop, at leastpart of the cells being input cells, the multiplexing circuit of eachinput cell comprising a further input coupled to the functional input,the multiplexing circuit being arranged to couple the functional inputto the scan outputs in the input cells in the further mode if the inputcell is selected to be a second one of the cells.
 7. An integratedcircuit according to claim 5, wherein each cell has a functional inputcoupled to an input of the scan flip-flop, at least part of the cellsbeing input cells, the multiplexing circuit of each input cellcomprising a further input coupled to the functional input, themultiplexing circuit being arranged to couple the functional input to aninput of the scan flip-flop and an output of the scan flip-flop to thescan output in the further mode if the cell is selected to be a secondone of the cells.
 8. An integrated circuit according to claim 5, whereineach cell has a functional output, and wherein at least part of thecells are output cells, the multiplexing circuit of each output cellbeing arranged to couple the functional output to the scan output in theoutput ones of the cells in the further mode if the output cell isselected to be a second one of the cells.
 9. An integrated circuitaccording to claim 5, wherein each cell has a functional output, atleast part of the cells being output cells, comprising an output circuitcoupled between the scan flip-flop and the functional output, the outputcircuit of each output cell being arranged to output data received fromthe shift register structure at the functional output in the furthermode if the cell is selected to be a second one of the cells and toprevent data from the shift register structure from being output at thefunctional output in the further mode if the cell is selected to be afirst one of the cells.
 10. An integrated circuit according to claim 9,wherein each cell comprises an update flip-flop coupled between theshift register structure and the output circuit, the output circuitoutputting data signals latched into the update flip-flop from theupdate flip-flop to the functional output in the further mode if thecell is selected to be a second one of the cells.
 11. An integratedcircuit according to claim 9, wherein the output circuit outputs datasignals continuously from the shift register structure to the functionaloutput in the further mode if the cell is selected to be a second one ofthe cells.
 12. An integrated circuit according to claim 9, wherein theoutput circuit of each output cell has a multiplexing function andmultiplex inputs are coupled to the functional input of the cell and tothe shift register structure, the output circuit coupling the functionalinput to the functional output in the further mode if the cell isselected to be a first one of the cells.
 13. An integrated circuitaccording to claim 1, wherein each cell comprises a scan flip-flop, thescan flip-flops of successive cells in the boundary scan chain beingcoupled in series in the shift register structure, the control circuitsupporting an instruction for switching the integrated circuit toasynchronous operation in said further mode, the first ones of the cellscreating a transparent path bypassing the scan flip-flops of the firstones of the cells in the shift register structure in asynchronousoperation, such that data are being directly written or read to or fromthe terminals from or to the shift register structure in the second onesof the cells in asynchronous operation.
 14. An integrated circuitaccording to claim 13, the control circuit supporting a furtherinstruction for switching the integrated circuit to synchronousoperation in said further mode, a length of the boundary scan chainbeing adapted in that the first ones of the cells are made transparentalong the shift register structure in the synchronous mode.
 15. Anintegrated circuit according to claim 1, wherein each cell comprises ascan flip-flop, the scan flip-flops of successive cells in the boundaryscan chain being coupled in series in the shift register structure, thecontrol circuit supporting an instruction for switching the integratedcircuit to synchronous operation in said further mode, a length of theboundary scan chain being adapted in that the first ones of the cellsare made transparent in the shift register structure in the synchronousmode.
 16. An integrated circuit according to claim 1, wherein thecontrol circuit comprises a state machine defining a plurality of stateswhich the state machine assumes under the control of a test protocol inthe test mode and which determine control signals issued to controlinputs of the cells for controlling the cells, said test protocol beingused to control the state machine also in the further mode, each cellhaving further control inputs for receiving a control signal thatindicates whether the integrated circuit operates in the further modeand a configuration signal that distinguishes whether cells function asa first one of the cells or a second one of the cells, for controllingthe cell with the control signals issued to the inputs in combinationwith the control signal and the configuration signal.
 17. An integratedcircuit according to claim 16, wherein the states include a shift statein which the control circuit controls the cells to shift data throughthe shift register structure in the test mode, the cells being arrangedsuch that the second ones of the cells transport the data that has beenor will be transported through the first ones of the cells in the shiftstate between the scan chain and the terminals or the core circuit whenthe state machine is in the shift state.
 18. An electronic circuit,comprising an integrated circuit according to claim 1 and one or morefurther integrated circuits coupled to the terminals of the integratedcircuit, wherein test inputs and outputs of the integrated circuits arecoupled in a daisy chain, and test control inputs of the integratedcircuits are coupled in parallel.
 19. A method of operating anelectronic circuit that comprises an integrated circuit and a furthercircuit coupled to each other, the integrated circuit comprising aboundary scan chain with cells coupled between a test data input andoutput of the integrated circuit in a shift register structure, eachcell being also coupled between a respective one of terminals of theintegrated circuit and a core circuit of the integrated circuit, theintegrated circuit being switchable to a functional mode, in which thecells permit signal flow between the terminals and the core circuit, toa test mode, in which test data is shifted serially through the cellsalong the boundary scan chain and in which the cells intercept signalflow between the respective ones of the terminals and the core circuit,and upon an instruction, to a further mode in which selectable firstones of the cells transport data serially along the boundary scan chainwhile selectable second ones of the cells write or read data that hasbeen or will be transported through the first ones of the cells in thefurther mode to or from the terminals from or to the scan chain, whereinthe method comprises a step of: switching the integrated circuit to thefurther mode and supplying and/or extracting successive signals toand/or from selected ones of the terminals through the boundary scanchain, while not transporting signals through the scan chain for or fromother ones of the terminals intervening between the successive signals.20. A method according to claim 19, wherein a particular one of thecells is configured to be a second one of the cells, all other cellsthat precede said particular one of the cells along the boundary scanchain from the test data input being configured to be first ones of thecells.
 21. A method according to claim 19, wherein a particular one ofthe cells is configured to be a second one of the cells, all other cellsthat succeed said particular one of the cells along the boundary scanchain to the test data output being configured to be first ones of thecells (14).
 22. A method according to claim 19, wherein an input one ofthe cells and an output one of the cells that succeeds the input one ofthe cells directly or indirectly along the boundary scan chain areconfigured to be second ones of the cells, any intervening cells betweenthe input one of the cells and the output one of the cells all beingconfigured to be first ones of the cells.
 23. A method according toclaim 19, comprising a bypassing of the cells coupled to said other onesof the terminals in the scan chain and supplying the successive signalsasynchronously from a clock for serial transport through the shiftregister structure.